The present invention relates to an electric circuit device which has a processor operating in accordance with a program and which is provided with an improved cartridge connection circuit for removably mounting a cartridge in which an external circuit is built.
In word processors, printers, personal computers and like information processing devices, a processor provided therein operates in accordance with a program which is stored in a memory built in the device main unit (which may also called an electric circuit), or the like.
However, it often happens that a cartridge with an external memory is used for expanding the memory space. In certain occasions, optional programs are stored in the cartridge's external memory. In these cases, the cartridges are removaly mounted to a connector provided on the device.
FIG. 1 shows a block diagram of a prior art cartridge connection circuit.
In the figure, a program cartridge 1 is connected to a main unit 2 via a connector 8. A read-only memory (ROM) 4 comprising several chips is built in or mounted on the program cartridge 1, and a decoder 5 is also provided to select one of these chips.
The main unit 2 is provided with a processor (CPU) 6 which controls various circuits, not shown, and operates in accordance with the programs stored in the program cartridge 1. By means of address signals 11, the processor 6 reads certain data 12 from the read-only memory 4 mounted on the program cartridge 1, and operates in accordance with the sequence and algorithm indicated by the data.
A decoder 7 is provided to control the access to other memories built in or mounted on the main unit 2. Moreover, a reset circuit 8 is provided to control resetting when the power supply to the device is turned on, or an operator instructs resetting by manipulation of a key.
The above circuits operates as follows.
First, when a program cartridge 1 is connected to the connector 3, a power supply line 20 and a ground line 20' are connected between the main unit 2 and the program cartridge 1. In this state, If the processor 6 outputs address signals 11, they are decoded by the decoder 7. As a result, the decoder 7 produces a select signal 13 to operate the decoder 5 mounted on the program cartridge 1.
When the decoder 5 starts its operation, it decodes the address signals 11 inputted from the main unit 2, and outputs a chip select signal for selecting one of the chips forming the read-only memory 4. One of the chips of the read-only memory 4 is thereby selected, and the address signal from the processor 6 is Inputted there.
The processor 6 supplies the selected chip with an output enable signal 15 for the reading of data. As a result, the selected chip of tile read-only memory 4 outputs data and permits the processor 6 to read the data.
When the power supply to tile main unit is turned on, the reset circuit 8 supplies the processor 6 with a reset signal 16 for a predetermined time. The reset signal 16 is terminated after a predetermined time, by a timer built In the reset circuit 8. Responsive to the termination of the reset signal 16, the processor starts the data reading operation and the like as described above.
Thus, by providing program cartridges 1 with read-only memories 4 storing different programs, different processings can be achieved by changing the program cartridge 1.
However, when power to the device shown in FIG. 1 Is turned on without a cartridge 1 mounted on the connector 3, because the processor 6 does not have a program to read, the processor 6 may behave erratically (i.e., the processor 6 operates out of control of a program). To avoid the erratic behavior when the program cartridge 1 is exchanged, it was necessary to turn off tile power during the exchange. This was troublesome.
FIG. 2 shows a block diagram of another prior art electric circuit device designed to solve the above problem.
In this device as well, a program cartridge 1 is connected to the main unit 2 via connector 3. A read-only memory 4, a decoder 5, a processor 6, a decoder 7, and a reset circuit 8 have a construction similar to those shown in FIG. 1.
In this device, a read-only memory 9 and a tri-state buffer 10 are added. A pull-up resistor R0 is connected to the input of the tri-state buffer 10, so that when a program cartridge 1 is not mounted, the input of the tri-state buffer 10 goes High. When a program cartridge 1 is mounted, the input of the tri-state buffer 10 goes Low due to input of a connection detection signal 21 from the program cartridge 1.
In FIG. 2, the processor 6 causes the decoder 7 to produce a chip select signal 17 for controlling the reading of the read-only memory 9. It simultaneously outputs an output enable signal 15 and supplies it to the read-only memory 9 to read data 12 from the read-only memory 9. The data 12 includes a program for judging the presence or absence of the connection detection signal 21 that is inputted to the tri-state buffer 10. In accordance with the program, the processor 6 makes a control signal 18 supplied from the decoder 7 to the tri-state buffer 10 low, to receive the connection detection signal 21 that is inputted to the tri-state buffer 10, via the data line 19. The processor 6 reads the connection detection signal 21 and judges whether or not a program cartridge 1 is mounted depending on whether the connection detection signal 21 is High or Low.
If no program cartridge 1 is mounted, the processor 6 receives data from the read-only memory 9 for terminating the operation in a predefined sequence. In tills way, the processor 6 is prevented from behaving erratically even if no program cartridge 1 is mounted.
When a program cartridge 1 is mounted, in the same way as described with reference to FIG. 1, a select signal 13 is supplied from the decoder 7 to the decoder 5, and a program is read from tile read-only memory 4.
As has been described, with the device of FIG. 2, a connection detection signal 21 is received from the program cartridge, so that when the program cartridge i is not mounted this is detected by the processor, and its erratic behavior is prevented.
However, with the device shown in FIG. 2, the read-only memory 9 is included in the logical address space of the processor 6. That is, part of the memory space of the processor 6 is occupied by the read-only memory 9, and the memory space formed of the read-only memory 4 of the program cartridge 1 is reduced. As a result, freedom in the design of the control program is reduced.